1. Field of the Invention
The present invention relates generally to processors, and in particular to methods and mechanisms for implementing return address stacks in processors.
2. Description of the Related Art
A typical processor utilizes a return address stack (RAS) for storing the address from which a program will fetch the next instruction when returning from a function call. In most stretches of a program, instructions may be executed sequentially from contiguous locations in memory. At some point, a call instruction may be executed to jump to a function, and instructions may be fetched from the memory location of the function. When the function has completed, the program will need to return to its previous place in memory for fetching instructions. Therefore, the return address is stored onto a RAS when a call instruction is executed. Typically the return address is the next address following the call instruction.
Maintaining the accuracy of a RAS can be challenging when processors support out-of-order execution of instructions, especially for load and store memory operations. Processors generally include support for load and store memory operations to facilitate transfer of data between the processors and memory. A load memory operation (or, more briefly, a load) is a memory operation specifying a transfer of data from a memory to the processor (although the transfer may be completed in cache). A store memory operation (or, more briefly, a store) is a memory operation specifying a transfer of data from the processor to memory. Loads and stores may be an implicit part of an instruction which includes a memory operation, or may be explicit instructions. In an out-of-order machine, when loads and stores execute speculatively, it is possible that a load instruction may need to be re-executed if a previous store to the same address is delayed. Accordingly, it is possible for the execution RAS to be corrupted with erroneous data due to instructions being re-executed.